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rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 1 - 512kx36 & 1mx18 synchronous pipelined sram the attached data sheets are prepared and approved by samsung electronics. samsung electr onics co., ltd. reserve the right to change the specifications. samsun g electronics will evaluate and reply to y our requests and questions on the parameter s of this device. if you have any questions, please contact the sams ung branch office near your office, call or cortact headquar ters. revision history rev. no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 0.3 remark advance advance advance final history - initial document - absolute maximum ratings are changed v dd : 2.815 - > 3.13 v ddq : 2.815 - > 2.4 v term : 2.815 - > vddq+0.5 (2.4v max) - recommended dc operating conditions are changed v ref / v cm -clk : 0.68 - > 0.6, 0.95 - > 0.9 - dc characteristics is changed i sbzz : 150 - > 128 - ac characteristics are changed t avkh / t dvkh / t wvkh / t svkh : 0.4 / 0.5 / 0.5 - > 0.3 / 0.3 / 0.3 t khax / t khdx / t khwx / t khsx : 0.5 / 0.5 / 0.5 - > 0.5 / 0.6 / 0.6 - recommended dc operating condition is changed max v dif-clk : v ddq +0.3 -> v ddq +0.6 - correct typo v dd -> v ddq : in mode control at page4 draft date dec. 2001 oct. 2002 jan. 2003 sep. 2003 document title
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 2 - pin description pin name pin description pin name pin description k, k differential clocks v ref hstl input reference voltage san synchronous address input m 1 , m 2 read protocol mode pins ( m 1 =v ss , m 2 =v ddq ) dqn bi-directional data bus g asynchronous output enable sw synchronous global write enable ss synchronous select sw a synchronous byte a write enable tck jtag test clock sw b synchronous byte b write enable tms jtag test mode select sw c synchronous byte c write enable tdi jtag test data input sw d synchronous byte d write enable tdo jtag test data output zz asynchronous power down zq output driver impedance control v dd core power supply v ss gnd v ddq output power supply nc no connection 512kx36 & 1mx18 sync hronous pipelined sram features organization part number maximum frequency access time 512kx36 k7p163666a-hc33 333mhz 1.5 k7p163666a-hc30 300mhz 1.6 k7p163666a-hc25 250mhz 2.0 1mx18 K7P161866A-hc33 333mhz 1.5 K7P161866A-hc30 300mhz 1.6 K7P161866A-hc25 250mhz 2.0 functional block diagram sa[0:18] or sa[0:19] ck ss sw sw x g 512kx36 data in zz dqx[1:9] (x=a, b, c, d) or (x=a, b) (x=a, b, c, d) or (x=a, b) k k ck or 1mx18 array row decoder column decoder write/read circuit register 0 1 data out register 1 read address register write address register latch sw register sw register latch sw x register sw x register ss register ss register 0 ? 512kx36 or 1mx18 organizations. ? 2.5v core/1.5v output power supply (1.9v max v ddq ). ? hstl input and output levels. ? differential, hstl clock inputs k, k . ? synchronous read and write operation ? registered input and registered output ? internal pipeline latches to support late write. ? byte write capability(four byte write selects, one for each 9bits) ? synchronous or asynchronous output enable. ? power down mode via zz signal. ? programmable impedance output drivers. ? jtag 1149.1 compatible test access port. ? 119(7x17)pin ball grid array package(14mmx22mm).
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 3 - package pin configurations (top view) k7p163666a(512kx36) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc sa 18 sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqc 8 dqc 9 v ss zq v ss dqb 9 dqb 8 e dqc 6 dqc 7 v ss ss v ss dqb 7 dqb 6 f v ddq dqc 5 v ss g v ss dqb 5 v ddq g dqc 3 dqc 4 sw cncsw bdqb 4 dqb 3 h dqc 1 dqc 2 v ss nc v ss dqb 2 dqb 1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd 1 dqd 2 v ss kv ss dqa 2 dqa 1 l dqd 3 dqd 4 sw dk sw adqa 4 dqa 3 m v ddq dqd 5 v ss sw v ss dqa 5 v ddq n dqd 6 dqd 7 v ss sa 0 v ss dqa 7 dqa 6 p dqd 8 dqd 9 v ss sa 1 v ss dqa 9 dqa 8 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc nc sa 14 sa 16 sa 3 nc zz u v ddq tms tdi tck tdo nc v ddq K7P161866A(1mx18) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc sa 19 sa 9 nc sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqb 1 nc v ss zq v ss dqa 9 nc e nc dqb 2 v ss ss v ss nc dqa 8 f v ddq nc v ss g v ss dqa 7 v ddq g nc dqb 3 sw bnc nc ncdqa 6 h dqb 4 nc v ss nc v ss dqa 5 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb 5 v ss kv ss nc dqa 4 l dqb 6 nc nc k sw adqa 3 nc m v ddq dqb 7 v ss sw v ss nc v ddq n dqb 8 nc v ss sa 0 v ss dqa 2 nc p nc dqb 9 v ss sa 1 v ss nc dqa 1 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc sa 18 sa 14 nc sa 3 sa 16 zz u v ddq tms tdi tck tdo nc v ddq
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 4 - the k7p163666a and K7P161866A are 18,874,368 bit synchronous pipeline mode sram. it is organized as 524,288 words of 36 bits(or 1,048,576 words of 18 bits)and is impl emented in samsungs advanced cmos technology. single differential hstl level k clocks are used to initiate the read/write ope ration and all internal operations are self-time d. at the updated from output registers edge of the next rising edge of the k clock. an internal write data buffer allows write data to f ollow one cycle after addresses and controls. the package is 119(7x17 ) ball grid array with balls on a 1.27mm pitch. during reads, the address is registered duri ng the frist clock edge, the internal array is read between this first edge and the second edge, and data is captured in the output register and driven to the cpu during the second clock edge. ss is driven low during this cycle, signaling that the sram should drive out the data. during consecutive read cycles where the addres s is the same, the data output must be held constant without any glitches. this characteristic is because the sram will be read by devices that will operate slower than the sram frequency and will require mu lti- ple sram cycles to perform a single read operation. write (stire) operation all addresses and sw are sampl ed on the clock rising edge. sw is low on the rising clock. write data is sampled on the rising clock, one cycle after write address and sw have been sampled by the sram. ss will be driven low during the same cycle that the address, sw and sw [a:d] are valid to signal that a valid ope ration is on the address and control input. pipelined write are supported. this is done by using write data buf fers on the sram that capture the write addresses on one wri te cycle, and write the array on the next write cycle. the "next wr ite cycle" can actually be many cycles away, broken by a serie s of read cycles. byte writes are suppor ted. the byte write signals sw [a:d] signal which 9-bit byte s will be writen. timing of sw [a:d] is the same as the sw signal. bypass read operation since write data is not fully written into the array on first wr ite cycle, there is a need to s ense the address in case a futur e read is to be done from the location that has not been written yet. for this case , the address comparator check to see if the new read addres s is the same as the contents of the stored write address latch. if the contents match, the read data must be supplied from the stor ed write data latch with standard read timing. if there is no match, th e read data comes from the sram array. the bypassing of the sram array occurs on a byte by byte basis . if one byte is written and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the sram array. mode control there are two mode control select pins (m 1 and m 2 ) used to set the proper read protocol. th is sram supports single clock pipelined operating mode. for proper s pecified device operation, m 1 must be connected to v ss and m 2 must be connected to v ddq . these mode pins must be set at power-up and must not change during device operation. programmable impedance output buffer operation this hstl late write sram has been designed with programm able impedance output buffers. the srams output buffer impedance can be adjusted to match the system data bus impedance, by connecti ng a external resistor (rq) between the zq pin of the sram and v ss . the value of rq must be five times the value of t he intended line impedance driven by the sram. for example, a 250 ? resistor will give an output buffer impedance of 50 ? . the allowable range of rq is from 175 ? to 350 ? . internal circuits evaluate and periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. one evalu- ation occurs every 32 clo ck cycles, with each evaluation moving the output bu ffer impedance level only one step at a time towar d the optimum level. impedance updates occur when the sram is in hi gh-z state, and thus are triggered by write and deselect operation s. updates will also be triggered with g high initiated high-z st ate, providing the specified g setup and hold times are met. impe dance match is not instantaneous upon power-up. in order to guarantee opt imum output driver impedance, the sram requires a minimum number of non-read cycles (1,024) after power-up. the output bu ffers can also be programmed in a minimum impedance configura- tion by connecting zq to v ss or v dd . power-up/power-down supply voltage sequencing the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simult aneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynchr onous zz pin high. during sleep mode, all other inputs are igno red and outputs are brought to a high-impedance state. sleep mode current and output high-z are guaranteed after the specified slee p mode enable time. during sleep mode the memory array data content is preserved. sleep mode must not be initiated until after al l pending operations have completed, as any pending operation is not gu aranteed to properly complete after sleep mode is initiate d. normal operations can be resumed by bri nging the zz pin low, but only after t he specified sleep mode recovery time. read operation function description
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 5 - function description the k7p163666a and K7P161866A are 18,874,368 bit dual mode (supports both register register and late select mode) sram devices. they are organized as 524,288 words by 36 bits for k7p163666a and 1,048,576 words by 18 bits for K7P161866A, fabri- cated using samsung's advanced cmos technology. late write/pi pelined read(rr) for x36/x18 organizations and late write/late select read(ls) for x36 organization are supported. the chip is operated with a single +2.5v power supply and is co mpatible wtih hstl input and output. the package is 119(7x17) plastic ball grid array with balls on a 1.27mm pitch. during read operations, addresses and contro ls are registered during the first risi ng edge of k clock and then the internal arr ay is read between first and second edges of k clock. data outputs ar e updated from output registers off the second rising edge of k clock. write operation(late write) during write operations, addresses including the way select addr ess(sas) and controls are registered at the first rising edge o f k clock and data inputs are registered at the following rising edge of k clock. write addresses and data inputs are stored in the data in registers until the next write operation, and only at the next wr ite opeation are data inputs fully written into sram array. by te write operation is supported using sw [a:d] and the timing of sw [a:d] is the same as the sw signal. bypass read operation since write data is not fully written into the array on first wr ite cycle, there is a need to sense the address in case a futur e read is to be done from the location that has not been written yet. for this ca se, the address comparator check to see if the new read addres s is the same as the contents of the stored write address latch. if the contents match, the read data must be supplied from the stor ed write data latch with standard read timing. if there is no match, t he read data comes from the sram array. the bypassing of the sram array occurs on a byte by byte basis. if one byte is wri tten and the other bytes are not, read data from the last written will have new byte data from the write data buffer and the other bytes from the sram array. mode control there are two mode control select pins (m 1 and m 2 ) used to set the proper read protocol. th is sram supports single clock pipelined operating mode. for proper specified device operation, m 1 must be connected to v ss and m 2 must be connected to v dd . these mode pins must be set at power-up and must not change during device operation. programmable impedance output buffer operation this hstl late write sram has been designed with programm able impedance output buffers. the srams output buffer impedance can be adjusted to match the system data bus impedance, by connect ing a external resistor (rq) between the zq pin of the sram and v ss . the value of rq must be five times the value of the in tended line impedance driven by the sram. for example, a 250 ? resistor will give an output buffer impedance of 50 ? . the allowable range of rq is from 175 ? to 350 ? . internal circuits evaluate and periodically adjust the output buffer impedance, as the impedanc e is affected by drifts in supply voltage and temperature. one evalu- ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time towar d the optimum level. impedance updates occur when the sram is in high- z state, and thus are triggered by write and deselect operation s. updates will also be triggered with g high initiated high-z stat e, providing the specified g se tup and hold times are met. impe dance match is not instantaneous upon power-up. in order to guarantee optimum output driver impedance, the sram requires a minimum number of non-read cycles (1,024) after power-up. the output buffers can also be programmed in a minimum impedance configura- tion by connecting zq to v ss or v dd . power-up/power-down supply voltage sequencing the following power-up supply voltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simult aneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynch ronous zz pin high. during sleep mode, all other inputs are igno red and outputs are brought to a high-impedance state. sleep mode current and output high-z are guaranteed after the specified slee p mode enable time. during sleep mode the memory array data content is preserved. sleep mode must not be initiated until after al l pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiate d. normal operations can be resumed by bringing the zz pin low, but only after the specified sleep mode recovery time. read operation for register register mode(x36 and x18) during read operations, addresses(sa) and contro ls except the way select address(sas) are registered during the first rising ed ge of k clock. the internal array(x72 bit data) is read between the first edge and the second edge, and as the way select address( sas) is registered at the second clock edge, x36 bit data is mux selected before the output register. read operation for late select mode(x36)
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 6 - truth table note : k & k are complementary k zz g ss sw sw a sw b sw c sw d dqa dqb dqc dqd operation xhxxxxxxxhi-zhi-zhi-zhi-zpower down m ode. no operation xlhxxxxxxhi-zhi-zhi-zhi-zoutput disabled. l lhxxxxxhi-zhi-zhi-zhi-zoutput disabled. no operation l l lhxxxxd out d out d out d out read cycle l x l l h h h h hi-z hi-z hi-z hi-z no bytes written lxlllhhhd in hi-z hi-z hi-z write first byte lxllhlhhhi-zd in hi-z hi-z write second byte l x l l h h l h hi-z hi-z d in hi-z write third byte l x l l h h h l hi-z hi-z hi-z d in write fourth byte lxlllllld in d in d in d in write all bytes absolute maximum ratings stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spe cification is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.13 v output supply voltage relative to v ss v ddq -0.5 to 2.4 v voltage on any i/o pin relative to v ss v term -0.5 to v ddq +0.5 (2.4v max) v output short-circuit current i out 25 ma operating temperature t opr 0 to 70 c storage temperature t stg -55 to 125 c recommended dc operating conditions parameter symbol min typ max unit note core power supply voltage v dd 2.37 2.5 2.63 v output power supply voltage v ddq 1.4 1.5 1.9 v input high level v ih v ref +0.1 - v ddq +0.3 v input low level v il -0.3 - v ref -0.1 v input reference voltage v ref 0.60.750.9 v clock input signal voltage v in -clk -0.3 - v ddq +0.3 v clock input differential voltage v dif -clk 0.1 - v ddq +0.6 v clock input common mode voltage v cm -clk 0.6 0.75 0.9 v
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 7 - dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 ? rq 350 ? . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 ? rq 350 ? . 5. programmable impedance output buffer mode. the zq pin is connected to v ss through rq. 6. minimum impedance output buffer mode. the zq pin is connected to v ss or v dd . parameter symbol min max unit note average power supply operating current-x36 (v in =v ih or v il , zz & ss =v il ) i dd33 i dd30 i dd25 - 700 620 550 ma 1, 2 average power supply operating current-x18 (v in =v ih or v il , zz & ss =v il ) i dd33 i dd30 i dd25 - 650 570 500 ma 1, 2 power supply standby current (v in =v ih or v il , zz=v ih ) i sbzz - 128 ma 1 active standby power supply current (v in =v ih or v il , ss =v ih , zz=v il ) i sbss - 200 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 a output leakage current (v out =v ss or v ddq , dq in high-z) i lo -1 1 a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v3,5 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4,5 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v6 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 6 output high voltage(i oh =-6ma) v oh3 v ddq -0.4 v ddq v6 output low voltage(i ol =6ma) v ol3 v ss 0.4 v 6 pin capacitance note : periodically sampled and not 100% tested.(t a =25 c, f=1mhz) parameter symbol test condition min max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 8 - ac test conditions (t a =0 to 70 c, v dd =2.37 -2.63v, v ddq =1.5v) note : parameters are tested with rq=250 ? and v ddq =1.5v. parameter symbol value unit core power supply voltage v dd 2.37~2.63 v output power supply voltage v ddq 1.5 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 0.5/0.5 ns input and out timing reference level 0.75 v clock input timing reference level cross point v 50 ? 50 ? ac test output load 25 ? 5pf dq v ddq /2 5pf v ddq /2 50 ? 50 ? v ddq /2 ac characteristics parameter symbol -33 -30 -25 unit note min max min max min max clock cycle time t khkh 3.0 - 3.3 - 4.0 - ns clock high pulse width t khkl 1.2 - 1.3 - 1.6 - ns clock low pulse width t klkh 1.2 - 1.3 - 1.6 - ns clock high to output valid t khqv -1.5-1.6-2.0ns clock high to output hold t khqx 0.5 - 0.5 - 0.5 - ns address setup time t avkh 0.3 - 0.3 - 0.3 - ns address hold time t khax 0.5 - 0.6 - 0.6 - ns write data setup time t dvkh 0.3 - 0.3 - 0.3 - ns write data hold time t khdx 0.5 - 0.6 - 0.6 - ns sw , sw [a:d] setup time t wvkh 0.3 - 0.3 - 0.3 - ns sw , sw [a:d] hold time t khwx 0.5 - 0.6 - 0.6 - ns ss setup time t svkh 0.3 - 0.3 - 0.3 - ns ss hold time t khsx 0.5 - 0.6 - 0.6 - ns clock high to output hi-z t khqz -1.5-1.6-2.0ns clock high to output low-z t khqx1 0.5 - 0.5 - 0.5 - ns g high to output high-z t ghqz -1.5-1.6-2.0ns g low to output low-z t glqx 0.5 - 0.5 - 0.5 - ns g low to output valid t glqv -1.5-1.6-2.0ns zz high to power down(sleep time) t zze -15-15-15ns zz low to recovery(wake-up time) t zzr -20-20-20ns
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 9 - timing waveforms of normal active cycles (ss controlled, g =low) 1234 5678 k san ss sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a 4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 1 d 3 d 4 q 5 q 4 timing waveforms of normal active cycles (g controlled, ss =low) 1234 5678 k san g sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 2 q 1 d 3 d 4 q 5 q 4 q 2 t khkh t khax t avkh t khkl t klkh t khsx t svkh t wvkh t khwx t wvkh t khwx t khqx1 t khqx t wvkh t khwx t khqv t khdx t khqz t dvkh t khdx t khkh t ghqz t glqx t glqv
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 10 timing waveforms of standby cycles 12345678 k san ss sw sw x dqn zz a 2 a 1 a 2 a 3 q 1 q 2 q 1 a 1 t khkh t zze t zzr t khqv t khqv
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 11 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction does not places dqs in hi-z. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 1 0 1 bypass bypass register 3 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access port and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo m 2 m 1 tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag fu nctions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in confor m- ance with ieee 1149.1, the sram contains a tap controller, instru ction register, bypass register and id register. the tap contr ol- ler has a standard 16-state machine that resets internally upon pow er-up, therefore, trst signal is not required. it is possibl e to use this device without utilizing the tap. to disable the tap contro ller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected.
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 12 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 512kx36 0000 00111 00100 xxxxxx 00001001110 1 1mx18 0000 01000 00011 xxxxxx 00001001110 1 boundary scan exit order(x36) 36 3b sa 9 sa 8 5b 35 37 2b sa 18 sa 17 6b 34 38 3a sa 10 sa 7 5a 33 39 3c sa 11 sa 6 5c 32 40 2c sa 12 sa 5 6c 31 41 2a sa 13 sa 4 6a 30 42 2d dqc 9 dqb 9 6d 29 43 1d dqc 8 dqb 8 7d 28 44 2e dqc 7 dqb 7 6e 27 45 1e dqc 6 dqb 6 7e 26 46 2f dqc 5 dqb 5 6f 25 47 2g dqc 4 dqb 4 6g 24 48 1g dqc 3 dqb 3 7g 23 49 2h dqc 2 dqb 2 6h 22 50 1h dqc 1 dqb 1 7h 21 51 3g sw c sw b5g 20 52 4d zq g 4f 19 53 4e ss k4k18 54 4g nc* k 4l 17 55 4h nc* sw a5l 16 56 4m sw dqa 1 7k 15 57 3l sw d dqa 2 6k 14 58 1k dqd 1 dqa 3 7l 13 59 2k dqd 2 dqa 4 6l 12 60 1l dqd 3 dqa 5 6m 11 61 2l dqd 4 dqa 6 7n 10 62 2m dqd 5 dqa 7 6n 9 63 1n dqd 6 dqa 8 7p 8 64 2n dqd 7 dqa 9 6p 7 65 1p dqd 8 zz 7t 6 66 2p dqd 9 sa 3 5t 5 67 3t sa 14 sa 2 6r 4 68 2r sa 15 sa 16 4t 3 69 4n sa 0 sa 1 4p 2 70 3r m 1 m 2 5r 1 boundary scan exit order(x18) 26 3b sa 9 sa 8 5b 25 27 2b sa 19 sa 17 6b 24 28 3a sa 10 sa 7 5a 23 29 3c sa 11 sa 6 5c 22 30 2c sa 12 sa 5 6c 21 31 2a sa 13 sa 4 6a 20 dqa 9 6d 19 32 1d dqb 1 33 2e dqb 2 dqa 8 7e 18 dqa 7 6f 17 34 2g dqb 3 dqa 6 7g 16 dqa 5 6h 15 35 1h dqb 4 36 3g sw b 37 4d zq g 4f 14 38 4e ss k4k13 39 4g nc k 4l 12 40 4h nc sw a5l 11 41 4m sw dqa 4 7k 10 42 2k dqb 5 dqa 3 6l 9 43 1l dqb 6 44 2m dqb 7 dqa 2 6n 8 45 1n dqb 8 dqa 1 7p 7 zz 7t 6 46 2p dqb 9 sa 3 5t 5 47 3t sa 14 sa 2 6r 4 48 2r sa 15 49 4n sa 0 sa 1 4p 3 50 2t sa 18 sa 16 6t 2 51 3r m 1 m 2 5r 1 scan register definition part instruction register bypass register id register boundary scan 512kx36 3 bits 1 bits 32 bits 70 bits 1mx18 3 bits 1 bits 32 bits 51 bits note :1. pins 4g and 4h are no connection pin to internal chip . the scanned data are fixed to "0" and "1" respectively. 1 1
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 13 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 2.37 2.5 2.63 v input high level v ih 1.7 - v dd +0.3 v input low level v il -0.3 - 0.8 v output high voltage(i oh =-2ma) v oh 2.1 - v dd v output low voltage(i ol =2ma) v ol v ss -0.2v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 7. parameter symbol min unit note input high/low level v ih /v il 2.5/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 1.25 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
rev 0.3 K7P161866A 512kx36 & 1mx18 sram k7p163666a sep. 2003 - 14 119 bga package dimensions 0.750 0.15 1.27 1.27 12.50 0.10 0.60 0.10 0.60 0.10 1.50ref c1.00 c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset : 0.10 max. 3. pcb to cavity offset : 0.10 max. indicator of ball(1a) location 119 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja tbd c/w 1w heating junction to case theta_jc tbd c/w junction to board theta_jb tbd c/w 2w heating

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